Abstract image representing MAPT chapter 9

Design, Modeling, Test, and Standards

Design, Modeling, Test, and Standards

Chapter 9 (Design, Modeling, Test, and Standards) is a crosscut that deals with future design automation portfolios and development of industry standards. These design tools and standards will give chip and system designers wings to explore and optimize across different design domains and metrics of performance, power/energy, area/volume, security, and safety, and will be the key enabler for the semiconductor industry.

Chapter contributors

Mitchell Heins (Synopsys) – Chair
Min Tsao (Siemens EDA) – Vice Chair
David Landsman (Western Digital) –Vice Chair
Ashraf Alam (Purdue University)
Abjhit Chatterjee (Georgia Tech)

Antonio de la Serna (Siemens EDA)
Farimah Farahmandi (University of Florida)
Yousef Iskander (Microsoft)
Steve Hoover (Redwood EDA)
Mohamed Kassem (eFabless)

Sung-Kyu Lim (Georgia Tech)
Patrick Madden (SUNY Binghamton)
Mary Ann Maher (Softmems)
Ming Zhang (PDF Solutions)